The present invention relates to integrated circuit data storage circuits, and more particularly, to SEU hardening circuits for use with integrated circuit data storage circuits. The military and orbital/interplanetary space markets have created a need for electronic systems that can operate in high radiation environments. Most applications for these systems also require high performance, high complexity, high density, and very low power. This produces a need for state-of-the-art technologies that are radiation hardened, i.e., have a tolerance or immunity to radiation effects. Other equivalent phrases include radiation hard or rad-hard.
Radiation can interact with many semi-conductor materials, including silicon based semi-conductor materials. These interactions can cause undesirable effects during circuit operation. For example, radiation can change the conductance of a MOS transistor by changing the threshold voltage (V.sub.t). Many of these undesirable effects can be minimized by using a radiation hardened process. However, in Very Large Scale Integration (VLSI) circuits, radiation can also generate significant levels of transient voltage and current disturbances on internal nodes, including power and ground. These internal disturbances can slow circuit performance or even upset circuit operation, e.g., changing the stored state of a data storage circuit. Simply having a radiation hardened process is often not adequate to suppress these type of effects.
It is common practice to characterize the sensitivity of a circuit using four main categories including: (1) total dose; (2) dose rate; (3) Single Event Upset (SEU); and (4) neutron. The present invention is primarily directed toward reducing the sensitivity of a data storage circuit to Single Event Upsets, and can also increase the dose rate hardness of the circuit. The data storage circuit may be a latch, register, a memory cell, or any other type of data storage circuit.
Orbital/interplanetary space is a relatively severe single event upset (SEU) environment. SEU is caused by energetic particles traversing through circuit nodes and depositing sufficient charge to disrupt circuit operation. Heavy particles are considered the dominating cause for data upsets. Heavy particles are capable of depositing relatively large amounts of charge on a circuit node. The particle distribution of concern is typically random, homogeneous in three-dimensional space, with a relatively small flux. Because of this particle distribution, the act of actually striking any particular circuit node is defined as a probability per unit time, which then correlates to a single event upset rate. A single event upset is an introduced error that can be corrected and is therefore generally called a soft error. The rate at which the soft errors accumulate is called the soft error rate (SER) and is equivalent to the single event upset rate. If the circuit of interest has more than one sensitive node, the SER for each node is summed to define the total SER for the circuit.
For a given node within a data storage circuit, there is typically a maximum deposited charge that a driving transistor or transistors (and nodal capacitance) can absorb while still maintaining the data storage circuit in the desired state. If the radiation-induced charge exceeds the maximum charge threshold, a change in the stored data state can result. Typically, each data storage circuit has one or more nodes that are most sensitive to radiation-induced charge. The maximum charge threshold for the most sensitive node or nodes is called the critical charge of the data storage circuit.
A data storage circuit typically includes a regenerative feedback path, e.g. a bi-stable element that is formed from two cross-coupled inverters, such as found in a memory cell. To maintain a desired data state during a radiation event, the n-channel transistor of one of the inverters must maintain a low data state on the output of that inverter, and the p-channel transistor of the other inverter must maintain a high data state on the output of the other inverter. In many data storage circuits, the transistors are of a minimum size to maximize density and minimize power.
To evaluate the SER of a data storage circuit, it is necessary to consider the maximum current carrying capability of the transistors. When a heavy ion traverses a node within the data storage circuit, it may force the node from its original state to the opposite state for some period of time. This is due to the charge that the heavy ion deposits as it passes through the silicon. If this node is held in the opposite state for a period longer than the delay around the data storage circuit feedback loop, the cell may switch states and the data may be lost.
The length of time that a node is held in its opposite state depends on three main factors. These factors include the total charge deposited on the node, the conductance of the data storage circuit transistors connected to the node, and the delay around the feedback loop of the data storage circuit. One way to reduce the chance of having an upset is to increase the conductance of the transistors (and therefore increase the size of the transistors). However, this increases the size of the data storage circuit, which is often undesirable particularly in large RAM-type memories where the data storage circuit (i.e. memory cell) is duplicated many times. Another way to reduce the chance of having an upset is to increase the feedback delay around the data storage circuit. By increasing the feedback delay, the "on" transistor is given more time to remove the deposited charge before the voltage state change can propagate sufficiently around the data storage circuit to establish the regenerative feedback path and result in a data upset.
The feedback delay can be increased by inserting resistors into the data storage circuit in a cross-coupled configuration. A RAM-type data storage circuit having two cross-coupled resistors is shown in FIG. 1. Cross-coupled resistors have proven effective in increasing the critical charge of a data storage circuit. However, because the resistors increase the delay around the data storage circuit feedback loop, the time required to deliberately write the data storage circuit is also increased. For a typical SEU requirement, the resistors must be of a size that increases the write time by as much as 5.times.relative to the write time of the data storage circuit without the cross-coupled resistors. This can be a significant performance penalty.
Another limitation of using cross-coupled resistors is that the material of choice is often polysilicon, often with a sheet resistance of about 100 k-ohm/square. In this region, the temperature coefficient of the polysilicon material is typically large. The temperature coefficient can cause write times to change radically with temperature. In the past, write time increases were acceptable in view of the increased SEU hardness. However, as system memory sizes increase, lower SER's are necessary, and the resulting write time increases are becoming unacceptable from a system perspective.
In another approach, the feedback delay around the data storage circuit can be increased by inserting cross-coupled transistors, which are then turned on during a write operation. A RAM-type data storage circuit having two cross-coupled transistors is shown in FIG. 2. The source of each cross-coupled transistor is connected to the output of one of the data storage circuit inverters. The drain of each cross-coupled transistor is connected to the input of the other one of the data storage circuit inverters. Finally, the gate of each cross-coupled transistor is connected to a word line.
The operation of the cross-coupled transistor cell is much the same as that of a standard data storage circuit with the following exception. When the word line is high, i.e. the cell is selected, the resistance of the cross-coupled transistor is low because the transistors are "on". Thus, the cell can be written relatively quickly. When the word line is low, the resistance of the cross-coupled transistors is high because the transistors are "off" Thus, the cell may have improved SEU hardness to heavy ion hits.
To function properly, the cross-coupled transistors must typically be sufficiently "leaky" when turned "off" to ensure that the data storage circuit remains in the desired state without requiring refresh. This is often accomplished by introducing a resistive element (see FIGS. 3-4) in parallel with the cross-coupled transistors. The resistive element must be large enough to provide the necessary SEU hardness for the data storage circuit. When the data storage circuit is written, the resistive element is shorted out by the cross-coupled transistor.
When using a bulk-technology, the cross-coupled transistor approach may have a number of limitations. The body terminal of the cross-coupled transistors typically cannot be effectively isolated from the power supply potentials. This increases the SEU sensitive area, i.e., the sensitive cross sectional area of nodes A and A' in FIG. 2. The sensitive area can be defined as any reversed biased junction, such that when a particle passes through the depiction region of the reversed biased junction, the deposited charge drifts and diffuses in a way that attempts to transition the voltage of the node to the opposite state.
In order to improve the SEU immunity, the resistance that is provided in parallel with the cross-coupled transistors must be at least 10-100.times. higher than the resistance of the inverter output nodes. Because A and A' are high impedance nodes, they will be easily discharged and held at ground (if the cross-coupled transistors are n-channel devices) or VDD (if the cross-coupled transistors are p-channel devices) when a SEU event strikes the body or junction thereof. This state change on the input to the inverter propagates through to its output node such that node A equals A', and the state of the data storage circuit becomes indeterminate.
One way to reduce the sensitive area within the cross-coupled transistors is to effectively isolate the body terminal from the power supply potentials, which is most easily done using an SOI technology. U.S. Pat. No. 5,631,863 to Fechner et al. discloses one such approach, and is generally shown in FIGS. 3-4 of the present specification. In Fechner et al., and referring to FIGS. 3-4, data storage circuit 10 includes an N-channel cross-coupled transistor 40, having source 46 connected to node 16, drain 48 connected to node 19 and gate 44 connected to word line 30. Data storage circuit 10 also includes N-channel cross-coupled transistor 42 having source 41 connected to node 18, drain 43 connected to node 17 and gate 45 connected to word line 30.
The body of the n-channel cross-coupled transistors 40 and 42 must be at the same potential as the source and drain terminals when the word line is turned off, i.e, in the SEU immune mode. This requires that the body be isolated relative to the normal well potentials experienced by the other transistors in the circuit. However, total isolation of the body leaves it floating and this is not desirable, since it can lead to circuit instability.
In order to reduce the instability caused by a floating body, Fechner et al. suggest providing a resistive contact R.sub.S between the body and the source, and a resistive contact R.sub.D between body and the drain. Using N-channel transistor 40 as an example, FIG. 4 shows resistive contact R.sub.S between the body 50 and the source 46, and the resistive contact R.sub.D between body 50 and the drain 48. FIG. 4 also shows top gate 44 of N-channel transistor 40, and the grounded parasitic backside gate 47 which results from the buried oxide layer of the illustrative SOI process. When transistor 40 is off, resistive contacts R.sub.S and R.sub.D provide a relatively large resistance path which sets S=B=D, leaving no reverse bias junctions and therefore no sensitive volumes. When transistor 40 is on, resistive contacts R.sub.S and R.sub.D are shorted out, allowing a relatively fast write time.
A limitation of Fechner et al. is that the resistance values of the resistive contacts R.sub.S and R.sub.D can be fairly limited. For example, Fechner et al. state that the resistance values should be sufficiently low to prevent parasitic drain-to-source bipolar gain effects, and sufficiently high to provide a desired level of SEU protection. These restrictions may ultimately limit the SEU protection that can be achieved. Another limitation of Fechner et al. is that the write times may be longer than optimal because the cross-coupled transistors 40 and 42 do not provide full rail drive during a write operation. While an increase in the write time can be seen in most data storage circuits with this SEU hardening approach, the most pronounced increase is often seen in data storage circuits that have only one side of the cross-coupled inverter pair driven during a write operation, such as a latch. In a memory cell, for example, both sides of the cross-coupled inverters are driven and the write time increase is less pronounced.